create_spice_validation_test_circuit.F90 18.1 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487

! This file is part of SACAMOS, State of the Art CAble MOdels in Spice. 
! It was developed by the University of Nottingham and the Netherlands Aerospace 
! Centre (NLR) for ESA under contract number 4000112765/14/NL/HK.
! 
! Copyright (C) 2016-2017 University of Nottingham
! 
! SACAMOS is free software: you can redistribute it and/or modify it under the 
! terms of the GNU General Public License as published by the Free Software 
! Foundation, either version 3 of the License, or (at your option) any later 
! version.
! 
! SACAMOS is distributed in the hope that it will be useful, but 
! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
! or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License 
! for more details.
! 
! A copy of the GNU General Public License version 3 can be found in the 
! file GNU_GPL_v3 in the root or at <http://www.gnu.org/licenses/>.
! 
! SACAMOS uses the EISPACK library (in /SRC/EISPACK). EISPACK is subject to 
! the GNU Lesser General Public License. A copy of the GNU Lesser General Public 
! License version can be found in the file GNU_LGPL in the root of EISPACK 
! (/SRC/EISPACK ) or at <http://www.gnu.org/licenses/>.
! 
! The University of Nottingham can be contacted at: ggiemr@nottingham.ac.uk
!
! File Contents:
! SUBROUTINE create_spice_validation_test_circuit
!
! NAME
!     create_spice_validation_test_circuit
!
! AUTHORS
!     Chris Smartt
!
! DESCRIPTION
!     This subroutine creates the Spice circuit model for the cable bundle
!     with the resistive terminations and voltage sources and the
!     simulation parameters i.e. a ready to run circuit file.
!
!     The process is as follows:
! STAGE 1: Open the circuit file, allocate memory and set up the node numbering
! STAGE 2: set up the circuit element names
! STAGE 3: write circuit elements to file 
! STAGE 3a: write circuit excitation voltage sources to file 
! STAGE 3b: write termination impedance networks
! STAGE 3c: write incident field excitation source if required
! STAGE 3d: write link to transmission line sub-circuit model
! STAGE 3e: write circuit outputs to file taking into accout the different spice syntaxes for output specifications 
! STAGE 4: close file and deallocate memory
!     
! COMMENTS
!     STAGE_1 Ngspice only
!     STAGE_4 Ngspice, Pspice and LTspice
!
! HISTORY
!
!     started 9/12/2015 CJS: STAGE_1 developments
!     22/4/2016 CJS: STAGE_4 developments: we can't use a common reference node at both ends now due to the d.c. resistances added into the
!                    transmission line sub-circuit so it has been changed 
!     15/6/2016 CJS: Incident field excitation requires a voltage to be supplied to two additional terminals on the multi-conductor sub-circuit
!                    interface to supply the incident field source function
!     24/8/2016 CJS: Change the writing format for the transmission line model subcircuit to remove long lines (this is a problem for Pspice)
!     12/3/2018 CJS: Add more header information about SACAMOS
!
!
SUBROUTINE create_spice_validation_test_circuit(spice_bundle_model,spice_validation_test)

USE type_specifications
USE general_module
USE constants
USE cable_module
USE cable_bundle_module
USE spice_cable_bundle_module

IMPLICIT NONE

! variables passed to the subroutine

TYPE(spice_model_specification_type),intent(IN) :: spice_bundle_model         ! spice bundle model information

TYPE(spice_validation_test_type),intent(IN)     :: spice_validation_test      ! spice validation test circuit information

! local variables

character(len=filename_length)    :: filename
character(len=filename_length)    :: spice_subcircuit_filename

integer :: n_conductors

! node numbering and component name stuff

integer :: node

! variables for external circuit, end 1
integer             :: end1_reference_node
integer,allocatable :: Vs_end1_nodes(:)                           ! conductor based end 1 voltage list
integer,allocatable :: R_end1_nodes(:)                           ! conductor based end 1 resistance list
character(len=spice_name_length),allocatable :: Vs_end1_name(:)   ! conductor based end 1 voltage source name list
character(len=spice_name_length),allocatable :: R_end1_name(:)   ! conductor based end 1 resistance name list

! variables for external circuit, end 2

integer             :: end2_reference_node
integer,allocatable :: Vs_end2_nodes(:)                           ! conductor based end 2 voltage list
integer,allocatable :: R_end2_nodes(:)                           ! conductor based end 2 resistance list
character(len=spice_name_length),allocatable :: Vs_end2_name(:)   ! conductor based end 2 voltage source name list
character(len=spice_name_length),allocatable :: R_end2_name(:)   ! conductor based end 2 resistance name list

! variables for incident field excitation source if requuired

integer :: Einc_node1
integer :: Einc_node2
character(len=spice_name_length) :: Einc_name

integer    :: output_node,output_reference_node
character(len=spice_name_length) :: output_node_name
character(len=spice_name_length) :: output_node_name2

character(len=spice_name_length) :: name1
character(len=spice_name_length) :: name2

integer,allocatable :: node_list(:)

! Resistance value to write

real(dp)   :: Rvalue

! loop variables
integer    :: row,col
integer    :: i

! START
  
! STAGE1: Open the circuit file, allocate memory and set up the node numbering

! open the file for the spice validation model - this goes in the current working directory...

  filename=trim(spice_bundle_model%spice_model_name)//test_circuit_file_extn
  
  OPEN(unit=test_circuit_file_unit,file=filename)

  write(*,*)'Opened file:',trim(filename)

! Allocate memory

  n_conductors=spice_bundle_model%bundle%tot_n_conductors

  ALLOCATE( Vs_end1_nodes(n_conductors) )
  ALLOCATE( R_end1_nodes(n_conductors) )
  ALLOCATE( Vs_end1_name(n_conductors) )
  ALLOCATE( R_end1_name(n_conductors) )
  
  ALLOCATE( Vs_end2_nodes(n_conductors) )
  ALLOCATE( R_end2_nodes(n_conductors) )
  ALLOCATE( Vs_end2_name(n_conductors) )
  ALLOCATE( R_end2_name(n_conductors) )

! set up the termination circuit nodes first, source end then load end.

  node=0
  end1_reference_node=node         ! this is the reference node for end 1 of the circuit (and the global reference node)
  
  node=node+1
  end2_reference_node=node         ! this is the reference node for end 2 of the circuit

  do row=1,n_conductors
    node=node+1
    Vs_end1_nodes(row)=node
  end do  

  do row=1,n_conductors   ! We cannot now use the same reference at both ends
    node=node+1
    Vs_end2_nodes(row)=node
  end do              
                              

  do row=1,n_conductors
    node=node+1
    R_end1_nodes(row)=node
  end do  

  do row=1,n_conductors
    node=node+1
    R_end2_nodes(row)=node
  end do  

  if (spice_bundle_model%include_incident_field) then

    node=node+1
    Einc_node1=node
    Einc_node2=end1_reference_node  ! i.e. the global reference node for the external circuit
  
  end if ! include_incident_field

! STAGE 2: set up the circuit element names

  do row=1,n_conductors
    name1='VS_'
    CALL add_integer_to_string(name1,row,Vs_end1_name(row))
  end do  

  do row=1,n_conductors
    name1='RS_'
    CALL add_integer_to_string(name1,row,R_end1_name(row))
  end do  

  do row=1,n_conductors
    name1='VL_'
    CALL add_integer_to_string(name1,row,Vs_end2_name(row))
  end do  

  do row=1,n_conductors
    name1='RL_'
    CALL add_integer_to_string(name1,row,R_end2_name(row))
  end do  

  if (spice_bundle_model%include_incident_field) then

    Einc_name='V_Einc'
  
  end if ! include_incident_field

! STAGE 3: write circuit elements to file

 if (spice_version.EQ.ngspice) then
    write(test_circuit_file_unit,'(A)')'Ngspice multi-conductor transmission line validation model'   
  else if (spice_version.EQ.LTspice) then
    write(test_circuit_file_unit,'(A)')'LTspice multi-conductor transmission line validation model'   
  else if (spice_version.EQ.Pspice) then
    write(test_circuit_file_unit,'(A)')'Pspice multi-conductor transmission line validation model'   
  end if ! spice version
  
  write(test_circuit_file_unit,'(A)')  '*'
  write(test_circuit_file_unit,'(A)')  '* Created by SACAMOS (State-of-the-Art CAble MOdels for Spice) '
  write(test_circuit_file_unit,'(A,A)')'* Spice cable model builder ',trim(SPICE_CABLE_MODEL_BUILDER_version)
  write(test_circuit_file_unit,'(A)')  '* www.sacamos.org'
  write(test_circuit_file_unit,'(A)')  '*'

  write(test_circuit_file_unit,'(A)')'* Voltage sources at end 1'
  
! STAGE 3a: write circuit excitation to file taking into accout the different spice syntaxes for output specifications 

  if (spice_validation_test%analysis_type.EQ.analysis_type_AC) then
 
    do row=1,n_conductors
! could specify magnitude AND phase here but use specified amplitude  and set phase to 0 at the moment
      write(test_circuit_file_unit,'(A20,2I6,A4,2ES16.6)')Vs_end1_name(row),Vs_end1_nodes(row),end1_reference_node,   &
                                                         ' AC ',spice_validation_test%Vs_end1(row),0.0
    end do

  else if (spice_validation_test%analysis_type.EQ.analysis_type_TRANS) then

    do row=1,n_conductors
     write(test_circuit_file_unit,'(A20,2I6,A,5ES16.6,A)')Vs_end1_name(row),Vs_end1_nodes(row),end1_reference_node,    &
                                      ' EXP( 0.0 ',spice_validation_test%Vs_end1(row),0.0,spice_validation_test%risetime, &
                                   spice_validation_test%width,spice_validation_test%risetime,' )'
    end do

  end if

  write(test_circuit_file_unit,'(A)')'* Voltage sources at end 2'

  if (spice_validation_test%analysis_type.EQ.analysis_type_AC) then

    do row=1,n_conductors
! could specify magnitude AND phase here but use specified amplitude  and set phase to 0 at the moment
      write(test_circuit_file_unit,'(A20,2I6,A4,2ES16.6)')Vs_end2_name(row),Vs_end2_nodes(row),end2_reference_node,  &
                                                         ' AC ',spice_validation_test%Vs_end2(row),0.0
    end do
  
  else if (spice_validation_test%analysis_type.EQ.analysis_type_TRANS) then

    do row=1,n_conductors
      write(test_circuit_file_unit,'(A20,2I6,A,5ES16.6,A)')Vs_end2_name(row),Vs_end2_nodes(row),end2_reference_node,    &
                                      ' EXP( 0.0 ',spice_validation_test%Vs_end2(row),0.0,spice_validation_test%risetime, &
                                   spice_validation_test%width,spice_validation_test%risetime,' )'
    end do
    
  end if
  
! STAGE 3b: write termination impedance networks

  write(test_circuit_file_unit,'(A)')'* Impedance network at end 1'
  
! note that the source impedance could be complex in the subroutine call - assumes a resistive diagonal matrix here...
  do row=1,n_conductors
    Rvalue=max(Rsmall,spice_validation_test%R_end1(row))
    write(test_circuit_file_unit,'(A20,2I6,ES16.6)')R_end1_name(row),R_end1_nodes(row),Vs_end1_nodes(row),Rvalue
  end do

  write(test_circuit_file_unit,'(A)')'* Impedance network at end 2'
  
! note that the load impedance could be complex in the subroutine call - assumes a resistive diagonal matrix here...
  do row=1,n_conductors
    Rvalue=max(Rsmall,spice_validation_test%R_end2(row))
    write(test_circuit_file_unit,'(A20,2I6,ES16.6)')R_end2_name(row),R_end2_nodes(row),Vs_end2_nodes(row),Rvalue
  end do

! STAGE 3c: write incident field excitation source if required
  if (spice_bundle_model%include_incident_field) then
  
    write(test_circuit_file_unit,'(A)')'* Incident field excitation source'

    if (spice_validation_test%analysis_type.EQ.analysis_type_AC) then

! could specify magnitude AND phase here but use specified amplitude  and set phase to 0 at the moment
      write(test_circuit_file_unit,'(A20,2I6,A4,2ES16.6)')Einc_name,Einc_node1,Einc_node2,  &
                                                         ' AC ',spice_bundle_model%Eamplitude,0.0
  
    else if (spice_validation_test%analysis_type.EQ.analysis_type_TRANS) then

      write(test_circuit_file_unit,'(A20,2I6,A,5ES16.6,A)')Einc_name,Einc_node1,Einc_node2,    &
                                      ' EXP( 0.0 ',spice_bundle_model%Eamplitude,0.0,spice_validation_test%risetime, &
                                   spice_validation_test%width,spice_validation_test%risetime,' )'

    end if
    
! include a resistance in series with the incident field voltage source to avoid a 'dangling' node

    write(test_circuit_file_unit,'(A7,2I6,A4)')'R_Einc ',Einc_node1,Einc_node2,' 1E6'
  
  end if ! include_incident_field

! Link to transmission line sub-circuit
  write(test_circuit_file_unit,'(A)')'* Link to transmission line sub-circuit'
  
! note: include voltage reference nodes now
  ALLOCATE( node_list(n_conductors) )
  write(test_circuit_file_unit,'(A)')'xtransmission_line'
  
  node_list(1:n_conductors)=R_end1_nodes(1:n_conductors)
  CALL write_long_node_list(n_conductors,node_list,max_spice_line_length,test_circuit_file_unit)
  
  node_list(1:n_conductors)=R_end2_nodes(1:n_conductors)
  CALL write_long_node_list(n_conductors,node_list,max_spice_line_length,test_circuit_file_unit)

  if (spice_bundle_model%include_incident_field) then
    write(test_circuit_file_unit,'(A,2I6)')'+',Einc_node1,Einc_node2
  end if
  write(test_circuit_file_unit,'(A,A)')'+',trim(spice_bundle_model%spice_model_name)

  spice_subcircuit_filename=trim(MOD_spice_bundle_lib_dir)//trim(spice_bundle_model%spice_model_name)//spice_model_file_extn

! include the transmission line subcircuit file here.
  write(test_circuit_file_unit,'(A)')'*'
  write(test_circuit_file_unit,'(A,A)')'.INCLUDE ',trim(spice_subcircuit_filename)
  write(test_circuit_file_unit,'(A)')'*'

! STAGE 3e: write circuit outputs to file taking into accout the different spice syntaxes for output specifications

! work out the output voltage node number
  if (spice_validation_test%output_end.eq.1) then
    output_node           =R_end1_nodes(spice_validation_test%output_conductor)
    output_reference_node =R_end1_nodes(spice_validation_test%output_conductor_ref)
  else
    output_node           =R_end2_nodes(spice_validation_test%output_conductor)
    output_reference_node =R_end2_nodes(spice_validation_test%output_conductor_ref)
  end if

  if (spice_validation_test%analysis_type.EQ.analysis_type_AC) then
    
! log frequency output
    if (spice_validation_test%analysis_freq_spec%freq_range_type.EQ.'log') then
      write(test_circuit_file_unit,'(A,I10,2ES16.6)')'.AC DEC ',   &
           NINT(spice_validation_test%analysis_freq_spec%n_frequencies/ &
                log10(spice_validation_test%analysis_freq_spec%fmax/spice_validation_test%analysis_freq_spec%fmin)), &
            spice_validation_test%analysis_freq_spec%fmin,spice_validation_test%analysis_freq_spec%fmax

    else         
! linear frequency output
      write(test_circuit_file_unit,'(A,I10,2ES16.6)')'.AC LIN ',   &
           spice_validation_test%analysis_freq_spec%n_frequencies, &
           spice_validation_test%analysis_freq_spec%fmin,          &
           spice_validation_test%analysis_freq_spec%fmax
    end if ! frequency range type
    
    write(test_circuit_file_unit,'(A)')'*'
  
    if (spice_version.EQ.Pspice) then
    
      name1='V('      
      CALL add_integer_to_string(name1,output_node,name2)
      if (spice_validation_test%output_end.eq.2) then
        name1=trim(name2)//','
        CALL add_integer_to_string(name1,output_reference_node,name2)
      end if
  
      output_node_name=trim(name2)//')'
    
      name1='VP('      
      CALL add_integer_to_string(name1,output_node,name2)
      if (spice_validation_test%output_end.eq.2) then
        name1=trim(name2)//','
        CALL add_integer_to_string(name1,output_reference_node,name2)
      end if
  
      output_node_name2=trim(name2)//')'
      write(test_circuit_file_unit,'(A,A,A,A)')'.PRINT ac  ',trim(output_node_name),' ',trim(output_node_name2)

    else ! ngspice or LTspice
    
      if (spice_validation_test%output_type.EQ.'li') then      
        if (plot_real) then
          name1='V('     
        else
          name1='VM('             
        end if 
      else if (spice_validation_test%output_type.EQ.'dB') then
        name1='VDB('         
      end if
  
      CALL add_integer_to_string(name1,output_node,name2)
  
      name1=trim(name2)//','
      CALL add_integer_to_string(name1,output_reference_node,name2)
  
      output_node_name=trim(name2)//')'
      write(test_circuit_file_unit,'(A,A)')'.PRINT ac  ',trim(output_node_name)
       
    end if
    
    if ( (spice_version.EQ.LTspice) .OR.(spice_version.EQ.Pspice) ) then
      write(test_circuit_file_unit,'(A)')'.PROBE'                      
    end if
    
  else 

! Transient simulation
    if (spice_validation_test%output_type.EQ.'li') then        
      name1='V('      
    else if (spice_validation_test%output_type.EQ.'dB') then
      name1='VDB('         
    end if
    CALL add_integer_to_string(name1,output_node,name2)
  
    name1=trim(name2)//','
    CALL add_integer_to_string(name1,output_reference_node,name2)
  
    output_node_name=trim(name2)//')'
    
    if (spice_version.NE.LTspice) then
      write(test_circuit_file_unit,'(A,2ES16.6)')'.TRAN ',    &
            spice_validation_test%timestep,spice_validation_test%runtime
    else
! Add a timestep limit for LTpsice
      write(test_circuit_file_unit,'(A,2ES16.6,A,ES16.6)')'.TRAN ',    &
            spice_validation_test%timestep,spice_validation_test%runtime,' 0.0 ',spice_validation_test%timestep/10d0
    end if
    
    write(test_circuit_file_unit,'(A)')'*'
    write(test_circuit_file_unit,'(A,A)')'.PRINT tran  ',output_node_name
    
    if (spice_version.EQ.Pspice) then
      write(test_circuit_file_unit,'(A)')'*'
      write(test_circuit_file_unit,'(A)')'.PROBE'                      
    end if

  end if

  write(test_circuit_file_unit,'(A)')'*'
  write(test_circuit_file_unit,'(A)')'*'
  write(test_circuit_file_unit,'(A)')'.END'

8100 format(10I4)

! STAGE 4: Close file and Deallocate memory

  CLOSE(unit=test_circuit_file_unit)

  write(*,*)'Closed file:',trim(filename)
  

  DEALLOCATE( Vs_end1_nodes)
  DEALLOCATE( R_end1_nodes )
  DEALLOCATE( Vs_end1_name )
  DEALLOCATE( R_end1_name )
  
  DEALLOCATE( Vs_end2_nodes )
  DEALLOCATE( R_end2_nodes )
  DEALLOCATE( Vs_end2_name )
  DEALLOCATE( R_end2_name )

  RETURN

END SUBROUTINE create_spice_validation_test_circuit