bjt-astable-npn.sch
2.64 KB
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v 20130925 2
C 40000 40000 0 0 0 title-A4.sym
C 47900 44600 1 0 0 npn-3.sym
{
T 47750 44900 5 10 1 1 0 0 1
refdes=Q2
T 47600 44650 5 10 1 1 0 0 1
value=BC548
}
C 45700 44600 1 0 1 npn-3.sym
{
T 45850 44900 5 10 1 1 0 6 1
refdes=Q1
T 45450 44650 5 10 1 1 0 0 1
value=BC548
}
C 45000 47300 1 270 0 resistor-2.sym
{
T 45300 46900 5 10 1 1 0 0 1
refdes=R1
T 45650 46750 5 10 1 1 180 0 1
value=22K
}
C 46200 47300 1 270 0 resistor-2.sym
{
T 46500 46900 5 10 1 1 0 0 1
refdes=R2
T 46950 46750 5 10 1 1 180 0 1
value=220K
}
N 45100 46400 45100 45600 4
N 46300 45100 47300 46000 4
N 47300 45100 46300 46000 4
N 48500 46400 48500 45600 4
N 48500 44600 48500 44400 4
N 48500 44400 45100 44400 4
N 45100 44600 45100 44400 4
N 45100 47500 48500 47500 4
C 46700 44100 1 0 0 gnd-1.sym
T 46000 40850 9 16 1 0 0 0 1
Astable Multivibrator
C 40550 40450 1 0 0 spice-model-1.sym
{
T 40650 41050 5 10 1 1 0 0 1
refdes=A1
T 41850 40750 5 10 1 1 0 0 1
model-name=BC548
T 41050 40550 5 10 1 1 0 0 1
file=../../lib/models/bc548.mod
}
C 47200 47300 1 270 0 resistor-2.sym
{
T 47750 47050 5 10 1 1 180 0 1
refdes=R3
T 47450 46650 5 10 1 1 0 0 1
value=220K
}
C 48400 47300 1 270 0 resistor-2.sym
{
T 48950 47050 5 10 1 1 180 0 1
refdes=R4
T 48650 46650 5 10 1 1 0 0 1
value=22K
}
N 45700 45100 46300 45100 4
N 46300 46400 46300 46000 4
N 47900 45100 47300 45100 4
N 47300 46400 47300 46000 4
C 42500 46400 1 0 0 vcc-1.sym
C 42500 46400 1 270 0 voltage-3.sym
{
T 43200 46200 5 8 0 0 270 0 1
device=VOLTAGE_SOURCE
T 43000 45900 5 10 0 1 0 0 1
refdes=Vcc
T 41800 45900 5 10 1 1 0 0 1
value=DC 3V
}
C 42600 45200 1 0 0 gnd-1.sym
C 46600 47500 1 0 0 vcc-1.sym
T 45100 40100 9 10 1 0 0 0 1
1
T 46600 40100 9 10 1 0 0 0 1
1
T 44900 40400 9 10 1 0 0 0 1
bjt-astable-npn.sch
T 49100 40400 9 10 1 0 0 0 1
2015 - 04 - 14
T 49100 40100 9 10 1 0 0 0 1
Mike Waters
T 45300 42000 9 10 1 0 0 0 4
Suggested setting for TR analysis :
Start time = 0.0 ms
Stop time = 200.0 ms
Step incr. = 100.0 us
T 45500 43300 9 10 1 0 0 0 1
Oscillation frequency = 33 Hz
T 40500 42200 9 10 1 0 0 0 2
This schematic can be simulated using
NG-Spice (last tested 2015-03-26).
C 45100 45800 1 0 0 capacitor-1.sym
{
T 45300 46500 5 10 0 0 0 0 1
device=CAPACITOR
T 45200 46100 5 10 1 1 0 0 1
refdes=C1
T 45300 46700 5 10 0 0 0 0 1
symversion=0.1
T 45700 46100 5 10 1 1 0 0 1
value=0.1uF
}
C 47300 45800 1 0 0 capacitor-1.sym
{
T 47500 46500 5 10 0 0 0 0 1
device=CAPACITOR
T 47400 46100 5 10 1 1 0 0 1
refdes=C2
T 47500 46700 5 10 0 0 0 0 1
symversion=0.1
T 47900 46100 5 10 1 1 0 0 1
value=0.1uF
}
N 46000 46000 46300 46000 4
N 48200 46000 48500 46000 4
N 45100 47500 45100 47300 4
N 46300 47300 46300 47500 4
N 47300 47500 47300 47300 4
N 48500 47300 48500 47500 4