\chapter{Using the Transmission Line models in Spice} \label{using_models_in_spice}

This chapter describes how the models, once created, can be used in the different versions of Spice supported, namely Ngspice, LTspice and Pspice.

If the GUI is being used to generate the spice cable bundle models then the path names indicated below may be set in the GUI so that the spice subcircuit files and the associated symbol files are copied to the appropriate directories. If Pspice is being used then there is a step using the Pspice model editor which is required to set up the model and symbol for use in schematic capture.


\subsection{Using Models in Ngspice}

The spice cable bundle model building process creates a subcircuit file \textbf{name.lib} and a corresponding symbol file \textbf{name.sym}.

For use by gshem the symbol file should be copied to the directory:

\textbf{ /usr/share/gEDA/sym/local}

When runnning the spice cable bundle model building process from the script \textbf{generate\_spice\_cable\_bundle\_model}, if you want to make the circuit symbols available for use by gshem you will need to add the following to the \textbf{generate\_spice\_cable\_bundle\_model} file:

SYMBOL\_DIR="/usr/share/gEDA/sym/local"

Note also that you may need to change ownership of SYMBOL\_DIR with something like the following command:    
sudo chown chris:chris /usr/share/gEDA/sym/local

The symbol file (\textbf{name.sym}) contains the path to the subcircuit library file for the transmission line model. The 
symbol file may require editing to ensure that the path is correct on any given system. The line which must be checked is

file=\textbf{$\backslash$PATH\_TO\_TRANSMISSION\_LINE\_SUB\_CIRCUITS/name.lib}

\subsection{Using Models in LTspice}
The spice cable bundle model building process creates a subcircuit file \textbf{name.lib} and a corresponding symbol file \textbf{name.asy}.

In order to use the subcircuit and the associated symbol in LTspice running on wondows, the symbol file, \textbf{name.asy}, should be copied into the LTspice symbol directory or a sub-directory created within this directory.

\textbf{ C:$\backslash$Program Files$\backslash$LTC$\backslash$LTspiceV$\backslash$lib$\backslash$sym   }

The symbol file contains the path to the subcircuit library file for the transmission line model. The 
symbol file may require editing to ensure that the path is correct on any given system. The line which must be checked is

SYMATTR ModelFile \textbf{ C:$\backslash$PATH\_TO\_TRANSMISSION\_LINE\_SUB\_CIRCUITS$\backslash$name.lib}

One this is set up correctly the symbol can be chosen and included in the schematic like any other.

\subsection{Using Models in Pspice}

The spice cable bundle model building process creates a subcircuit file \textbf{name.lib}. When using this model in Pspice there is an initial stage of creating a Cadence Pspice library file which includes an associated symbol. The process required is as follows:

\enumerate{

\item Start the Pspice model editor.

\item Load the subcircuit file (\textbf{name.lib}) using the model input wizard (file $\rightarrow$ Model Input Wizard). The dialog box automatically fills the name of the library file to be produced (\textbf{name.olb})

\item Reply 'Yes' to the question 'Do you want to attach the default rectangular symbol'. At this point the library file \textbf{name.olb} is produced.

\item If you would like the model to be available in the default libraries loaded then you will need to edit the file: 
\textbf{C:$\backslash$Cadence$\backslash$SPB\_17.2$\backslash$tools$\backslash$Pspice$\backslash$library$\backslash$normd.lib} to include the line

.lib "name.lib"

If this step is not done then the library file will have to loaded explicitly by editing the 'Simulation Settings' in Orcad Capture, before running the simulation.

}

The library will have to be loaded when placing parts in the schematic.

\subsection{Non-convergence issues in Spice and possible solutions}

It is not uncommon for Spice simulations to fail to run to completion 
due to non-convergence of the solution to the specified tolerances. This 
is a complicated issue due to the different solution algorithms which are
used in each of the Spice analysis options. The main converegence issues 
are related to the following:

\enumerate{
\item Newton Raphson algorithm for non-linear equations

\item D.C. bias point calculation

\item Transient Analysis

\item Timestep control
}

These aspects of Spice and the options available to change the Spice operation
to improve convergence are discussed for each. Note that not all options are
available in all versions of Spice. A detailed discussion of these issues is
found in reference \cite{Kielkowski}

\subsubsection{Newton Raphson algorithm}

The circuit equations are solved for non-linear circuit elements using
the Newton Raphson algorithm. The iteration stops when the following conditions
are satisfied:

1. For all the nodes in the circuit:
|V(t)-V(t-dt)| < RELTOL*V(t)+VNTOL

2 For all the branch currents in the circuit:
|I(t)-I(t-dt)| < RELTOL*I(t)+ABSTOL

RELTOL is a relative tolerance whose default value is 0.001
VNTOL has a default value of 1$\mu$V
ABSTOL has a default value of 1pA

If there is a convergence error in the Newton Raphson solution then it is worth
considering increasing VNTOL and/or ABSTOL. VNTOL can be set to a value RELTOL*Vsmall
where Vsmall is the smallest voltage of interest. Similarly, ABSTOL can be set to 
a value RELTOL*Ismall where Ismall is the smallest current of interest

Convergence may also be improved by increasing GMIN. This is the minimum conductance 
which is allowed between nodes. GMIN should be set to be as large as possible without
affecting the circuit operation i.e. work out the smallest resistance, R which can 
be connected between the circuit nodes then set GMIN=1/R.

If non-linear devices are included in the circuit then convergence may be improved by 
ensuring that non-linear models include some series resistance in the .MODEL definition.

\subsubsection{D.C. bias point calculation}

If Spice fails to find a d.c. bias point then the following actions may help:

1. Increase ITL1, the number of d.c. bias point iterations from the default of ITL1=100
to ITL1=500 (say)

2. Try to assist the d.c. convergence by setting some initial node values for the 
convergence calculation e.g.
.NODESET  V(n)=X

3. Use source stepping by setting ITL6 to 500 for example

\subsubsection{Transient Analysis}

In order to aid transient analysis, all non-linear device models should have their
associated capacitance values set to a non-zero value.

The number of iterations for convergence at a time point can also be increased 
for example set ITL4=40 (default value is 10). If this value is exceeded then 
the timestep is reduced. 

\subsubsection{Timestep control}

Automatic timestep control can aid convergence and speed of the solution
however there are some issues to be aware of.

1. The timestep is always less than the print interval (TSTEP) so this can be used
to set a limit on the timestep.

2. Increase ITL4 to prevent the timestep being reduced too readily. This may improve the
total simulation time. The default value is 10. 


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