* gnetlist -g spice-sdb -o 2_wire_ac.cir 2_wire_ac.sch
*********************************************************
* Spice file generated by gnetlist                      *
* spice-sdb version 4.28.2007 by SDB --                 *
* provides advanced spice netlisting capability.        *
* Documentation at http://www.brorson.com/gEDA/SPICE/   *
*********************************************************
*vvvvvvvv  Included SPICE model from /home/chris/ESA_CABLE_MODELLING_LOCAL/PROJECT/TEST_CASES/TWO_WIRE/RUN_DIRECTORY/2_wire_ac.lib vvvvvvvv
* Ngspice multi-conductor transmission line model subcircuit
*
* Cable bundle name: 2_wire
*
*
*Transmission line subcircuit 
*
.subckt  2_wire_ac     2     1     4     1
*
* Modal impedances: source end
*
RZCm_1                   2     3    0.227497E+03
*
* Modal impedances: load end
*
RZCm_2                   4     5    0.227497E+03
*
* Modal voltage controlled voltage source: source end
*
Em_1                     3     1    11     1    0.100000E+01
*
* Modal voltage controlled voltage source: load end
*
Em_2                     5     1    10     1    0.100000E+01
*
* Delay lines for positive z propagation, 
*
T_pz                    10     1     6     1 Z0=    0.227497E+03 TD=    0.667128E-08
*
* Delay lines for negative z propagation
*
T_mz                    11     1     8     1 Z0=    0.227497E+03 TD=    0.667128E-08
*
* Modal impedances: load end for pz propagation
*
RZC_pz                  10     1    0.227497E+03
*
* Modal impedances: load end for mz propagation, Tsource
*
RZC_mz                  11     1    0.227497E+03
*
* Delay line controlled sources for positive z propagation
*
E1_pz                    6     7     2     1    0.200000E+01
E2_pz                    7     1     3     1   -0.100000E+01
*
* Delay line controlled sources for negative z propagation
*
E1_mz                    8     9     4     1    0.200000E+01
E2_mz                    9     1     5     1   -0.100000E+01
*
.ends
*
*^^^^^^^^  End of included SPICE model from /home/chris/ESA_CABLE_MODELLING_LOCAL/PROJECT/TEST_CASES/TWO_WIRE/RUN_DIRECTORY/2_wire_ac.lib ^^^^^^^^
*
*==============  Begin SPICE netlist of main design ============
X? 1 0 3 0 2_wire_ac
Vs 2 0 ac 1 0
Rl 3 0 50.0  
Rs 2 1 50.0  
*
.AC DEC       1000    0.100000E+04    0.100000E+09
*
.PRINT ac  VM(1)               
.end