! This file is part of SACAMOS, State of the Art CAble MOdels in Spice. 
! It was developed by the University of Nottingham and the Netherlands Aerospace 
! Centre (NLR) for ESA under contract number 4000112765/14/NL/HK.
! 
! Copyright (C) 2016-2017 University of Nottingham
! 
! SACAMOS is free software: you can redistribute it and/or modify it under the 
! terms of the GNU General Public License as published by the Free Software 
! Foundation, either version 3 of the License, or (at your option) any later 
! version.
! 
! SACAMOS is distributed in the hope that it will be useful, but 
! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
! or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License 
! for more details.
! 
! A copy of the GNU General Public License version 3 can be found in the 
! file GNU_GPL_v3 in the root or at <http://www.gnu.org/licenses/>.
! 
! SACAMOS uses the EISPACK library (in /SRC/EISPACK). EISPACK is subject to 
! the GNU Lesser General Public License. A copy of the GNU Lesser General Public 
! License version can be found in the file GNU_LGPL in the root of EISPACK 
! (/SRC/EISPACK ) or at <http://www.gnu.org/licenses/>.
! 
! The University of Nottingham can be contacted at: ggiemr@nottingham.ac.uk
!
! File Contents:
! SUBROUTINE write_spice_dc_resistances
!
! NAME
!     write_spice_dc_resistances
!
! AUTHORS
!     Chris Smartt
!
! DESCRIPTION
!     write the d.c. resistances on each of the terminal conductors
!
!     INPUTS REQUIRED
!     1. The conductor based node numbers at the terminations of the bundle
!     2. A 1D array of d.c. resistance values
!     3. The first free node available
!     4. The reference node number
!    note that the last conductor is connected to the reference node
!     5. The bundle length
!
!     OUTPUTS
!     1. The components required to implement the model are written to
!        the subcircuit file
!     2. The nodes on the d.c. resistances are returned to the calling process for connection to the domain decomposition model
!     
! COMMENTS
!      note that the d.c. resistance of a conductor is split equally between the two ends
!
! HISTORY
!
!     STAGE 4 developments started 22/4/2016 CJS
!
SUBROUTINE write_spice_dc_resistances( vref_node,next_free_node,Rdc,n_conductors,end,external_nodes,rdc_nodes,length)
  
USE type_specifications
USE general_module
USE spice_cable_bundle_module

IMPLICIT NONE

! variables passed to the subroutine

  integer,intent(IN)     :: vref_node                       ! sub-circuit reference node number
  integer,intent(INOUT)  :: next_free_node                  ! next free spice subcircuit node number 
  integer ,intent(IN)    :: n_conductors                    ! total number of conductors
  real(dp),intent(IN)    :: Rdc(1:n_conductors)             ! d.c. resistance per unit length of conductor
  integer,intent(IN)     :: end                             ! end number of transmission line (1 or 2)
  integer,intent(IN)     :: external_nodes(1:n_conductors)  ! external node numbers for sub-circuit (these are known on input)
  integer,intent(OUT)    :: rdc_nodes(1:n_conductors)       ! node numbers on the d.c. resistance   (these generated here and returned)
  real(dp),intent(IN)    :: length                          ! length of conductor (m)

! local variables

  character(LEN=spice_name_length) :: name_head          ! head of the name for the d.c. resistance circuit elements
  character(LEN=spice_name_length) :: Rdc_name           ! full name for the d.c. resistance circuit elements, includes conductor and end number

  integer :: conductor   ! conductor loop variable

! START
   
  name_head='Rdc'

!loop over conductors  
  do conductor=1,n_conductors

! create the component name with the conductor and end number  
    CALL build_name_with_conductor_and_end(name_head,conductor,end,Rdc_name)
    
    if (conductor.NE.n_conductors) then
! create a new node
      rdc_nodes(conductor)=next_free_node
      next_free_node=next_free_node+1
    else
! connect the last conductor to the reference node for the transmission line model
      rdc_nodes(conductor)=vref_node
    end if

! Note that half the d.c. resistance of the bundle goes at each end    
    write(spice_model_file_unit,'(A30,2I6,ES16.6)')Rdc_name,external_nodes(conductor),rdc_nodes(conductor),Rdc(conductor)*length/2d0
     
  end do
    
  RETURN

END SUBROUTINE write_spice_dc_resistances