! This file is part of SACAMOS, State of the Art CAble MOdels in Spice. 
! It was developed by the University of Nottingham and the Netherlands Aerospace 
! Centre (NLR) for ESA under contract number 4000112765/14/NL/HK.
! 
! Copyright (C) 2016-2017 University of Nottingham
! 
! SACAMOS is free software: you can redistribute it and/or modify it under the 
! terms of the GNU General Public License as published by the Free Software 
! Foundation, either version 3 of the License, or (at your option) any later 
! version.
! 
! SACAMOS is distributed in the hope that it will be useful, but 
! WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
! or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License 
! for more details.
! 
! A copy of the GNU General Public License version 3 can be found in the 
! file GNU_GPL_v3 in the root or at <http://www.gnu.org/licenses/>.
! 
! SACAMOS uses the EISPACK library (in /SRC/EISPACK). EISPACK is subject to 
! the GNU Lesser General Public License. A copy of the GNU Lesser General Public 
! License version can be found in the file GNU_LGPL in the root of EISPACK 
! (/SRC/EISPACK ) or at <http://www.gnu.org/licenses/>.
! 
! The University of Nottingham can be contacted at: ggiemr@nottingham.ac.uk
!
! FILE CONTAINS (within include files):
!
!create_new_node.F90: 						SUBROUTINE create_new_node
!create_spice_subcircuit_model.F90: 				SUBROUTINE create_spice_subcircuit_model
!create_spice_subcircuit_symbol.F90: 				SUBROUTINE create_spice_subcircuit_symbol
!create_spice_validation_test_circuit.F90: 			SUBROUTINE create_spice_validation_test_circuit
!write_incident_field_excitation_circuit.F90: 			SUBROUTINE write_incident_field_circuit
!write_s_domain_controlled_voltage_source.F90: 			SUBROUTINE write_s_domain_controlled_voltage_source
!write_s_domain_controlled_voltage_source.F90: 			SUBROUTINE write_filter_model
!write_s_domain_controlled_voltage_source.F90: 			SUBROUTINE write_Pspice_filter_model
!write_spice_comment_line.F90: 					SUBROUTINE write_spice_comment
!write_spice_dc_resistances.F90: 				SUBROUTINE write_spice_dc_resistances
!write_spice_domain_decomposition_equivalent_circuit.F90:   	SUBROUTINE write_spice_domain_decomposition_equivalent_circuit
!write_spice_method_of_characteristics_equivalent_circuit.F90:  SUBROUTINE write_spice_method_of_characteristics_equivalent_circuit
!write_spice_modal_decomposition_equivalent_circuit.F90:   	SUBROUTINE write_spice_modal_decomposition_equivalent_circuit
!write_spice_subcircuit_header.F90: 				SUBROUTINE write_spice_subcircuit_header
!write_transfer_impedance_circuit.F90: 				SUBROUTINE write_transfer_impedance_circuit
!write_ZT_incident_field_excitation_circuit.F90: 		SUBROUTINE write_ZT_incident_field_circuit

!write_delay_line.F90: 		                                SUBROUTINE write_delay_line

! Name
!    create_spice_model
!
! Description
!     module which includes the subroutines relating to the creation of spice cable models
!
! Comments:
!      
!
! History
!
!     started 12/01/16 CJS

!     16/11/2017 CJS Include network synthesis process to replace s-domain transfer functions

!

MODULE create_spice_model

USE type_specifications

USE module_network_synthesis

IMPLICIT NONE

CONTAINS

include 'create_spice_subcircuit_model.F90'

include 'write_spice_subcircuit_header.F90'

include 'write_spice_dc_resistances.F90'

include 'write_spice_domain_decomposition_equivalent_circuit.F90'

include 'write_spice_modal_decomposition_equivalent_circuit.F90'

include 'write_spice_method_of_characteristics_equivalent_circuit.F90'

include 'write_transfer_impedance_circuit.F90'

include 'write_incident_field_excitation_circuit.F90'

include 'write_ZT_incident_field_excitation_circuit.F90'

include 'create_spice_subcircuit_symbol.F90'

include 'create_spice_validation_test_circuit.F90'

include 'write_s_domain_controlled_voltage_source.F90'

include 'write_spice_comment_line.F90'

include 'write_delay_line.F90'

include 'create_new_node.F90'

END MODULE create_spice_model